The fabrication of three-dimensional (3d) integrated circuits has been previously accomplished by several techniques. One approach employs a fabrication technology wherein active silicon films are grown in successive layers with intervening insulating layers. However, this approach must overcome difficult materials problems, and also generally precludes the testing of individual layers of the device. Furthermore, the total fabrication time is proportional to the number of layers, and becomes lengthy for a structure having more than three or four layers of active circuitry.
Another known approach involves the thinning and stacking of conventional integrated circuit dice into cubes, with additional processing to bring metal interconnects out to the edge of the cube. The cubes are then attached and electrically connected to a substrate by the use of solder bumps. However, this approach requires considerable handling of the small dice and therefore incurs high processing costs. Furthermore, all interconnects between the vertically stacked dice must be made at the edges. This tends to limit the operating speed by requiring additional lengths of conductors to bring the signals to and from the edges.
A third approach is described by Hayashi et al., "Fabrication of Three-Dimensional IC Using `Cumulatively Bonded IC` (CUBIC) Technology", 1990 Symposium on VLSI Technology, which employs a method of thinning and stacking integrated circuit functional blocks and incorporating vertical interconnects between adjacent functional blocks. A supporting substrate is employed to support a Si layer when a Si crystal is removed by a preferential polishing method. The supporting substrate is later removed. A perceived disadvantage to this approach is that the bulk silicon crystal is required to be mechanically thinned down, using a LOCOS-buried SiO.sub.2 as a polish stop. This process may be difficult to control in order not to remove the LOCOS-buried SiO.sub.2, and cannot be readily applied to technologies other than LOCOS-isolated CMOS. This process also appears to require that the LOCOS-buried SiO.sub.2 extend further into the Si than the active devices in the Si. This may present a serious limitation for many applications.
It is thus an object of this invention to overcome these and other problems of the prior art.
It is another object of this invention to provide a novel semiconductor fabrication technology to construct 3d integrated circuits of small volume by stacking Silicon-on-Insulator (SOI) integrated circuit wafers, wherein a silicon substrate is chemically etched away using the buried oxide as an etch stop.
A further object of this invention is to provide a fabrication technology that results in a 3d circuit that supports metal oxide semiconductor (MOS), bipolar, or combination technologies; and that achieves a high circuit density through the use of thin silicon films with small vertical feedthroughs.